Introduction

This blog will share some of the questions faced by VLSI - Front End Designers. (FPGA/ASIC) It will provide substantial answers for most of them. The Questions will try to cover the below areas:

• Digital Design
• RTL Design
• Synthesis
• Static Timing Analysis (STA)
• Clock domain crossing and Multi-clock Design
• ASIC/FPGA Design flow
• FPGA Architecture and Prototyping
• Logical reasoning

I will not be covering the definitions of basic concepts like, define FPGA/ASIC, setup/hold time, Mealy/Moore State Machine, etc., as it can be found in other websites. I would rather focus on other concepts which are based on these. This will surely help most of the VLSI Designers in preparing for interviews. Please post your valuable comments on improving this so that the purpose is served.


All the Best and hope this helps.




Regards,
Manju