VLSI Interview Questions - I

Lets start with simple questions. There will be a maximum of 3 questions per post.

Q1: What is the difference between SRAM and DRAM ?

A: Both are volatile memories.(data is lost when powered off) But, SRAM need not be periodically refreshed as compared to DRAM. DRAM stores each bit of data in a separate capacitor. It can either be charged or discharged. (either to 1 or 0).

Since capacitor leak charge, the data fades unless the capacitor is refreshed periodically.
This marks the difference between SRAM and DRAM.

Q2: Design a posedge/negedge/edge dectector circuit ?

A: Basically, edge detector circuits are used during bit synchronisation from one clock domain to the other. Below circuit will explain in detail:

Posedge detection circuit:

Below is the Waveform explaining explaining the circuit:

Negedge Detection circuit: 

Below is the Waveform explaining the circuit:

Edge detection circuit:

Below is the Waveform explaining the cicuit:

Introduction

This blog will share some of the questions faced by VLSI - Front End Designers. (FPGA/ASIC) It will provide substantial answers for most of them. The Questions will try to cover the below areas:

• Digital Design
• RTL Design
• Synthesis
• Static Timing Analysis (STA)
• Clock domain crossing and Multi-clock Design
• ASIC/FPGA Design flow
• FPGA Architecture and Prototyping
• Logical reasoning

I will not be covering the definitions of basic concepts like, define FPGA/ASIC, setup/hold time, Mealy/Moore State Machine, etc., as it can be found in other websites. I would rather focus on other concepts which are based on these. This will surely help most of the VLSI Designers in preparing for interviews. Please post your valuable comments on improving this so that the purpose is served.


All the Best and hope this helps.




Regards,
Manju